View TDA7503_1758533.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual 24-bit 40 mips dsp cores 8 bit microcontroller 4 receive and 5 transmit stereo channels of serial audio interface synchronous serial interface for communica- tion with external processor fifo based mailboxes for inter-processor communications external memory interface to 128kb sram or 1mb dram cordic co-processor programmable pll to suite wide range of ex- ternal crystal oscillation frequencies spi control interface powerful debug interfaces 1280 words program memory for dsp1, 768 words program memory for dsp0 256 words x and y data ram and data rom for each dsp 256 byte data ram for microcontroller 768 byte auxiliary ram for microcontroller description the device is a high-performance digital signal processing ic particularly suited to audio applica- tions. the device contains two 24-bit 40 mips dsp cores delivering a total of 80 mips of dsp processing power. there is also an embedded 8- bit microcontroller to handle all control functions. all data and program memories for both dsp cores are on-chip. a variety of highly programma- ble and flexible peripheral blocks for both the mi- crocontroller and the dsps have been integrated to form a powerful audio processing system on a single chip. this is preliminary information on a new product now in development. details are subject to change without notice. july 1999 ? host interface 0 debug interface dsp0 core m8051 core mi cro memory interface serial interface control interface aux-ram 768 bytes peripheral c ordic ari thmetic u nit pdb1 pab1 ydb1 yab1 xdb1 xab1 pdb0 pab0 ydb0 yab0 xdb0 xab0 mclk dsp1 core host interface 1 serial audio interface synchronous audio interface sram/ d ram interface xchg interface xdb0 xab0 xdb1 xab1 x-ram0 x-rom0 y-ram0 y-rom0 p-ram0 p-rom0 p-ram1 p-rom1 y-ram1 y-rom1 x-ram1 x-rom1 aux-ram 256 bytes watchdog timer pll clock oscillator dclk block diagram tqfp100 TDA7503 dual dsp plus micro for audio applications product preview 1/26
absolute maximum ratings symbol parameter value unit v ddc core dc supply voltage -0.5 to 5 v v ddp pads dc supply voltage -0.5 to 6.5 v v i ,v in digital or analog input voltage -0.5 to (v ddp +0.5) v t op operative temperature range -40 to 85 c t stg storage temperature range (plastic) -55 to 150 c thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient 85 c/w 1 2 3 5 6 4 7 8 9 10 45 11 46 47 48 49 50 86 85 84 83 81 82 80 79 78 77 76 70 69 68 66 65 67 75 74 73 71 72 mosi miso reset vddi3_core3 t1(p3.5) vssi3_core3 lrckr vdde5_ci1 vsse5_ci1 sclk ss/gpios sra_d7/dra3 sra_d6/dra2 sra_d5/dra1 sra_d4/dra0 vsse5_dr1 vdde5_dr1 sra_d3/drd3 sra_d2/drd2 sra_d1/drd1 sra_d0/drd0 sra12/dra8 rd(p3.7) wr(p3.6) xale rad0(p0.0) rad2(p0.2) rad1(p0.1) rad3(p0.3) rad4(p0.4) rad5(p0.5) rad6(p0.6) rad7(p0.7) xpsen ra11(p2.3) ra9(p2.1) ra13(p2.5) ra14(p2.6) ra8(p2.0) ra10(p2.2) vssi3_core4 vddi3_core4 vdde5_mi1 vsse5_mi1 d97au693 40 41 42 43 44 97 96 95 94 92 93 91 90 89 88 87 txd(p3.1) rxd(p3.0) gpio6(p1.6) gpio5(p1.5) gpio3(p1.3) gpio4(p1.4) vdde5_mi2 vsse5_mi2 gpio2(p1.2) gpio1(p1.1) gpio0(p1.0) 100 99 98 t0(p3.4) int0(p3.2) int1(p3.3) 34 35 36 37 38 39 xti filt pgnd pvcc scanen testen dbout dbck/os1 dbin/os0 dbrqn dbsel 29 30 31 32 33 vsse5_sa1 vdde5_sa1 xto 26 27 28 12 13 14 16 17 15 18 19 20 21 22 59 58 57 55 54 56 64 63 62 60 61 sdo4 sdi0 sdi1 sdi3 sclkr sdi2 vssi3_core2 sdo0 sdo1 sdo3 sdo2 sra9/dra5 vdde5_dr2 vsse5_dr2 sra13/ras vssi3_core1 sra8/dra4 ra15(p2.7) ra12(p2.4) sra10/dra6 sra11/dra7 drd 23 24 25 52 51 53 lrckt sclkt vddi3_core2 dwr ale/cas vddi3_core1 pin connection TDA7503 2/26
pin description n. name type reset status (1) function 11 lrckr i audio serial port receive left/right frame sync. the left/right select signal for received serial audio data. this signal has a frequency equal to the audio sample rate. 12 sclkr i audio serial port receive bit clock. sclk clocks received digital audio data into pins sdi0, sdi1, sdi2, and sdi3 16 sdi0 i stereo digital audio data. sdi0 is a stereo digital audio data input pin channel 0. 15 sdi1 i stereo digital audio data. sdi1 is a stereo digital audio data input pin channel 1. 14 sdi2 i stereo digital audio data. sdi2 is a stereo digital audio data input pin channel 2. 13 sdi3 i stereo digital audio data / serial receive data. sdi3 is a stereo digital audio data input pin and is multiplexed with the ssi's serial receive data input channel 3. 25 lrckt i audio serial port transmit left/right frame sync /frame sync. the left/right select signal for transmitted serial audio data. this signal has a frequency equal to the audio sample rate. this signal is multiplexed with the ssi's frame sync input. 24 sclkt i audio serial port transmit bit clock/ssi serial bit clock. sclk clocks digital audio data out of pins sdo0, sdo1, sd02, sd03, and sd04. this pin is multiplexed with the ssi's serial bit clock. 21 sdo0 o high stereo digital audio data. sdo0 is a stereo digital audio data output pin channel 0. 20 sdo1 o high stereo digital audio data. sdo1 is a stereo digital audio data output pin channel 1. 19 sdo2 o high stereo digital audio data. sdo2 is a stereo digital audio data output pin channel 2. 18 sdo3 o high stereo digital audio data. sdo3 is a stereo digital audio data output pin channel 3. 17 sdo4 o high stereo digital audio data /serial transmit data. sdo4 is a stereo digital audio data output pin and is multiplexed with the ssi's serial transmit data output channel 4. 34 scanen i scan enable. enable scan path and muxing of scanin and scanout pins. 33 testen i test enable. enable scan mode clocks. an active low signal will enable the same clock to all scan chains. this pin also makes all latches transparent. 49 sra_d0/drd0 i/o i dsp sram multiplexed address/data line 0/dsp dram data line 0.when in sram mode these pins act as the emi multiplexed address and data line 0. when in dram mode they act as the emi data line 0. 48 sra_d1/drd1 i/o i dsp sram multiplexed address/data line 1/dsp dram data line 1.when in sram mode these pins act as the emi multiplexed address and data line 1. when in dram mode they act as the emi data line 1. 47 sra_d2/drd2 i/o i dsp sram multiplexed address/data line 2/dsp dram data line 2.when in sram mode these pins act as the emi multiplexed address and data line 2. when in dram mode they act as the emi data line 2. 46 sra_d3/drd3 i/o i dsp sram multiplexed address/data line 3/dsp dram data line 3.when in sram mode these pins act as the emi multiplexed address and data line 3. when in dram mode they act as the emi data line 3. 43 sra_d4/dra0 i/o o, high dsp sram multiplexed address/data line 4/dsp dram address line 0. when in sram mode these pins act as the emi multiplexed address and data line 4. when in dram mode they act as the emi address line 0. TDA7503 3/26
n. name type reset status (1) function 42 sra_d5/dra1 i/o o, high dsp sram multiplexed address/data line 5/dsp dram address line 1. when in sram mode these pins act as the emi multiplexed address and data line 5. when in dram mode they act as the emi address line 1. 41 sra_d6/dra2 i/o o, high dsp sram multiplexed address/data line 6/dsp dram address line 2. when in sram mode these pins act as the emi multiplexed address and data line 6. when in dram mode they act as the emi address line 2. 40 sra_d7/dra3 i/o o, high dsp sram multiplexed address/data line 7/dsp dram address line 3. when in sram mode these pins act as the emi multiplexed address and data line 7. when in dram mode they act as the emi address line 3. 56 sra8/dra4 o high dsp sram address line 8/dsp dram address line 4. when in sram mode these pins act as the emi address line 8. when in dram mode they act as the emi address line 4. 59 sra9/dra5 o high dsp sram address line 9/dsp dram address line 5. when in sram mode these pins act as the emi address line 9. when in dram mode they act as the emi address line 5. 62 sra10/dra6 o high dsp sram address line 10/dsp dram address line 6. when in sram mode these pins act as the emi address line 10.when in dram mode they act as the emi address line 6. 60 sra11/dra7 o high dsp sram address line 11/dsp dram address line 7. when in sram mode these pins act as the emi address line 11. when in dram mode they act as the emi address line 7. 50 sra12/dra8 o high dsp sram address line 12/dsp dram address line 8. when in sram mode these pins act as the emi address line 12. when in dram mode they act as the emi address line 8. 55 sra13/ras o high dsp sram address line 13/dram row address strobe. when in sram mode this pin acts as the emi address lines 13. when in dram mode this pin acts as the row address strobe. 51 ale/cas o high dsp sram address latch enable/colomn address. when in sram mode this pin acts as the emi address latch enable. when in dram mode this pin acts as the column address strobe. 52 dwr o high dsp sram write enable/dram write enable. this pin serves as the write enable for the emi when in dram and sram modes. 61 drd o high dsp sram read enable/dram read enable. this pin serves as the read enable for the emi when in dram and sram modes. 36 dbck/os1 i/o i debug port bit clock/chip status 1. the serial clock for the debug port is provided when an input. when an output, together with os0 provides information about the chip status. can also be used as gpio for the 8051. 37 dbin/os0 i/o i debug port serial input/chip status 0. the serial data input for the debug port is provided when an input. when an output, together with os1 provides information about the chip status. can also be used as gpio for the 8051. 35 dbout i/o i debug port serial output. the serial data output for the debug port. can also be used as a gpio for the 8051. 38 dbrqn i debug port request input. means of entering the debug mode of operation. 39 dbsel i debug port mux selection. selects either dsp0 or dsp1 to be connected to the debug port pins. 67 ra8(p2.0) i/o i microcontroller high byte address lines. this pin is the address line 8 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. 68 ra9(p2.1) i/o i microcontroller high byte address lines. this pin is the address line 9 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. pin description (continued) TDA7503 4/26
n. name type reset status (1) function 75 ra10(p2.2) i/o i microcontroller high byte address lines. this pin is the address line 10 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. 69 ra11(p2.3) i/o i microcontroller high byte address lines. this pin is the address line 11 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. 63 ra12(p2.4) i/o i microcontroller high byte address lines. this pin is the address line 12 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. 66 ra13(p2.5) i/o i microcontroller high byte address lines. this pin is the address line 13 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. 65 ra14(p2.6) i/o i microcontroller high byte address lines. this pin is the address line 14 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. 64 ra15(p2.7) i/o i microcontroller high byte address lines. this pin is the address line 15 of a 16 bit address, for external eprom and memory mapped devices. it can also act as gpio using the p2 and p2dir registers. 83 rad0(p0.0) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 0 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 82 rad1(p0.1) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 1 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 81 rad2(p0.2) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 2 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 80 rad3(p0.3) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 3 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 79 rad4(p0.4) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 4 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 78 rad5(p0.5) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 5 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 77 rad6(p0.6) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 6 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 76 rad7(p0.7) i/o i microcontroller address/data pins. this pin is the multiplexed address and data line bit 7 for external eprom and memory mapped peripherals. it can also act as gpio using the p0 and p0dir registers. 84 xale i/o i microcontroller external address latch enable. this pin is the address latch enable. a logic high indicates that address/data lines 7 through 0 represent an address. inactive for program/data fetches from internal aux. 85 wr(p3.6) i/o i microcontroller write strobe. external data memory write strobe. this pin can also act as gpio using the p3 and p3dir registers. 86 rd(p3.7) i/o i microcontroller read strobe. external data memory read strobe. active low, or gpio. this pin can also act as gpio using the p3 and p3dir registers. disabled by setting the rdsel bit in the pinctl register. 70 xpsen i/o i microcontroller external program memory enable. external program memory enable pin. active low. changes functionality to rd when microcontroller is fetching instructions out of internal aux ram. controlled by the pssel and psbit bits in the pinctl register. pin description (continued) TDA7503 5/26
n. name type reset status (1) function 4 reset i/o i system reset. a logic low level applied to reset input initializes the microcontroller. the micro is responsible for initializing the dsps. if the watchdog timer overflow occurs this pin is driven low for 1 watchdog timer cycle. during debug mode if this pin is pulled low in while the dbrqn line is pulled low then the dsp pointed to by the dbsel pin will be reset. 96 rxd(p3.0) i/o i microcontroller standard serial interface (asynchronous) input data. or gpio. this pin can also act as gpio using the p3 and p3dir registers. 97 txd(p3.1) i/o i microcontroller standard serial interface (asynchronous) output data. or gpio. this pin can also act as gpio using the p3 and p3dir registers. 99 int0(p3.2) i/o i microcontroller interrupt 0. when pulled low, int0 asserts a microcontroller external interrupt. in addition, if this pin is pulled low during powerdown this allows the m8051 to resume executing intructions where it left off. this pin can also act as gpio using the p3 and p3dir registers. 98 int1(p3.3) i/o i microcontroller interrupt 1. when pulled low, int1 asserts a microcontroller external interrupt. in addition, if this pin is pulled low during powerdown this allows the m8051 to resume executing intructions where it left off. this pin can also act as gpio using the p3 and p3dir registers. 100 t0(p3.4) i/o i microcontroller timer 0 external input. input event clock for timer 0, or gpio. this pin can also act as gpio using the p3 and p3dir registers. 1 t1(p3.5) i/o i microcontroller timer 1 external input. input event clock for timer 1, or gpio. this pin can also act as gpio using the p3 and p3dir registers. 87 gpio0(p1.0) i/o i microcontroller general purpose. this gpio line can be configured to be digital input or output by writing to the p1 and p1dir registers.this pin is tri-stated while the reset pin is held low and is pulled low when reset is released. this pin will be pulled high when in idle or pwrdn modes. 88 gpio1(p1.1) i/o i microcontroller general purpose. this gpio line can be configured to be digital input or output by writing to the p1 and p1dir registers. at reset it is configured as an input with the output tri-stated. 89 gpio2(p1.2) i/o i microcontroller general purpose. this gpio line can be configured to be digital input or output by writing to the p1 and p1dir registers. at reset it is configured as an input with the output tri-stated. 92 gpio3(p1.3) i/o i microcontroller general purpose. this gpio line can be configured to be digital input or output by writing to the p1 and p1dir registers. at reset it is configured as an input with the output tri-stated. 93 gpio4(p1.4) i/o i microcontroller general purpose. this gpio line can be configured to be digital input or output by writing to the p1 and p1dir registers. at reset it is configured as an input with the output tri-stated. 94 gpio5(p1.5) i/o i microcontroller general purpose. this gpio line can be configured to be digital input or output by writing to the p1 and p1dir registers. at reset it is configured as an input with the output tri-stated. 95 gpio6(p1.6) i/o i microcontroller general purpose. this gpio line can be configured to be digital input or output by writing to the p1 and p1dir registers. at reset it is configured as an input with the output tri-stated. 7 sclk i/o i microcontroller general purpose. each of the six gpio lines can be individually configured to be digital input or output by writing to the p1 and p1dir registers. all gpios are configured to be inputs with the outputs tri-stated except for p1.0. this pin is tri-stated during while the reset pin is held low and is pulled low when reset is released. this pin will be pulled high when in idle or pwrdn modes. 6 mosi i/o i microcontroller spi master output slave input serial data . serial data output for spi type serial port when in spi master mode and serial data input when in spi slave mode. pin description (continued) TDA7503 6/26
n. name type reset status (1) function 5 miso i/o i microcontroller spi master input slave output serial data . serial data input for spi style serial port when in spi master mode and serial data output when in spi slave mode. 8 ss/gpios i/o i microcontroller spi slave select . slave select input for spi type serial port. this pin can be used as a gpio when the spi is disabled or in master mode. 32 pvcc i pll clock power supply . vdd pin for pll clock oscillator. 28 xto o high crystal oscillator output. crystal oscillator output drive. 29 xti i crystal oscillator input. external clock input or crystal connection. 30 filt o high pll loop filter capacitor output. capacitor connected between filt and xgnd establishes primary pll. 31 pgnd i pll clock ground input. ground connection for oscillator circuit. 53 vddi3_core1 pwr 3.3v core supply. 23 vddi3_core2 pwr 3.3v core supply. 2 vddi3_core3 pwr 3.3v core supply. 73 vddi3_core4 pwr 3.3v core supply. 54 vssi3_core1 gnd core ground. 22 vssi3_core2 gnd core ground. 3 vssi3_core3 gnd core ground. 74 vssi3_core4 gnd core ground. 27 vdde5_sa1 pwr 5v supply for sai pads. 26 vsse5_sa1 gnd ground for sai pads. 10 vdde5_ci1 pwr 5v supply for control interface pads. 9 vsse5_ci1 gnd ground for control interface pads. 71 vdde5_mi1 pwr 5v supply for micro memory interface pads. 91 vdde5_mi2 pwr 5v supply for micro memory interface pads. 72 vsse5_mi1 gnd ground for micro memory interface pads. 90 vsse5_mi2 gnd ground for micro memory interface pads. 44 vdde5_dr1 pwr 5v supply for dsp emi interface pads. 58 vdde5_dr2 pwr 5v supply for dsp emi interface pads. 45 vsse5_dr1 gnd ground for dsp emi interface pads. 57 vsse5_dr2 gnd ground for dsp emi interface pads. pin description (continued) TDA7503 7/26
recommended dc operating conditions symbol parameter test condition min. typ. max. unit v ddc 3.3v power supply voltage 3 3.3 3.6 v v ddp 5v power supply voltage 4.5 5 5.5 v tj operating junction temperature -40 125 c general interface electrical characteristics symbol parameter test condition min. typ. max. unit note i il low level input current without pull-up device v i =0v 1 m a1 i ih high level input current without pull-down device vi = v ddp 1 m a1 i oz tri-state output leakage without pullup/down device vo = 0v or v ddp 1 m a1 c in input capacitance 10 pf 2 i latchup i/o latch-up current v < 0v, v > v ddp 200 ma v esd electrostatic protection leakage < 1 m a 2000 v 3 note 1: the leakage currents are generally very small, < 1na. the value given here, 1ma, is a maximum that can occur after an electrostatic stress on the pin. note 2: guaranteed by design. note 3: human body model. dc electrical characteristics symbol parameter test condition min. typ. max. unit note v il low level input voltage 0.25 ? v ddp v v ih high level input voltage 0.7 ? v ddp v v ol low level output voltage i ol = 2ma 0.4 v 1 v oh high level output voltage i ol = -2ma v ddp -0.4 v 1 note 1: takes into account 200mv voltage drop in both supply lines. TDA7503 8/26
power consumption symbol parameter value unit p tot maximum current for core power supply @ 3.3v 320 ma note: 40mhz internal dsp clock at tamb external clocks (xti pin) the TDA7503 system clock is externally supplied via the xti pin. timings shown in this document are valid for clock rise and fall times of 3ns maximum. symbol characteristics value unit f ext max. frequency @ xti when pll is disabled 20 mhz when pll is enabled see constraints for internal clocks. internal clocks symbol characteristics expression f dsp_max maximum dsp internal operation frequency (dclk) 40mhz f m p_max maximum m p (8051) internal operation frequency (mclk) 20mhz f dsp internal dsp clock cycle frequency (dclk) mf ? f ext 2 ? df f m p inernal m p (8051) clock cycle frequency (mclk) mf ? f ext 4 ? df i cyc_dsp dsp machine cycle time dclk i cyc_ m p m p (8051) machine cycle time mclk/12 note 1 : if the dcksrc bit of the clock control register is 0 then dclk = fext/2. note 2 : if the mcksrc bit of the clock control register is 1 then mclk = fext else of mcksrc0 is 0 then mclk = fext/4. note 3 : df is pll input devide factor, bits idf [4:0] of pll control register one. note 4 : mf is pll multiply devide factor, bits mp [6:0] of pll control register zero. phase locked loop (pll) characteristics characteristics expression value unit vco frequency when pll enabled mf ? fext df 40 to 80 mhz recommended pll external capacitor (pin filt) 3.3 nf reset characteristics expression unit minimum reset assertion 100/fext ns TDA7503 9/26
tde lrckt left right left right internal flag set when left data written to all enabled transmitters. if this internal tde cleared when right data written to all enabled transmitters. flag is set then right data must written to data registers before the next rdr lrckr left right left right rdr cleared when right data read from all enabled transmitters. internal flag set when left data read from all enabled receivers. if this internal flag is set then right data must read from data registers before the next falling edge of lrckt. rising edge of lrckr. figure 2. sai interrupt protocol sdi0-3 lrckr sckr (rckp=0) t lrh t sdis t sdih t lrs t sckpl t sckph valid valid t dt t sckr sai/ssi interface figure 1. sai and ssi timings timing description value unit t sckr minimum clock cycle 3t dsp +5 ns t dt sckr active edge to data out valid 40 ns t lrs lrck setup time 5 ns t lrh lrck hold time 5 ns t sdid sdi setup time 5 ns t sdih sdi hold time 5 ns t sckph minimum sck high time 0.35 t sckr ns t sckpl minimum sck low time 0.35 t sckr ns note t dsp = dsp master clock cycle time = 1/f dsp TDA7503 10/26
left right lsb(n-1) msb(word n) msb-1 (n) msb-2 (n) lrckr sckr sdi0 figure 3. sai protocol when rlrs=0; rrel=0; rckp=1; rdir=0. left right msb(n-1) lsb(word n) lsb+1 (n) lsb+2 (n) lrckr sckr sdi0 figure 4. sai protocol when rlrs=1; rrel=0; rckp=1; rdir=1. left right lsb(n-1) msb(word n) msb-1 (n) msb-2 (n) lrckr sckr sdi0 figure 5. sai protocol when rlrs=0; rrel=0; rckp=0; rdir=0. lsb(n-1) msb(word n) msb-1 (n) msb-2 (n) left right lrckr sckr sdi0 figure 6. sai protocol when rlrs=0; rrel=1; rckp=1; rdir=0. TDA7503 11/26
five word packet data word frame sync 1 frame sync 0 data in sck receive network mode interrupts frame sync 1 frame sync 0 data in sck receive interrupts normal mode figure 7. ssi protocol. the timing diagrams for the ssi interface are shown in figure 7 for both network and normal modes. in normal mode the rising edge fsync starts the internal bit counter to allow data to be clocked in or out. when bit count is equal to the pro- grammed word length the counter is reset and the shift register is broadside loaded into the data register. additional sck pulses are ignored after the counter is reset. the next word is clocked in or out starting with the next rising edge of fsync. in network mode the rising edge fsync starts the internal bit counter to allow data to be clocked in or out. when bit count is equal to the pro- grammed word length the counter is reset and the shift register is broadside loaded into the data register. at this point the fsrsd bit is set indicat- ing that a frame sync was received with that word. after being reset the counter continues counting, clocking in the next word. only when the next rising edge of fsync is detected is the packet considered complete. TDA7503 12/26
spi interface symbol description min value unit master t sclk clock cycle mclk/12 m s t dtr sclk edge to mosi valid 40 m s t dts miso setup time 5 m s slave t sclk clock cycle mclk/6 m s t dtr sclk edge to mosi valid 40 m s t dts miso setup time 5 m s t sckph minimum sck high time mclk/12 m s t sckpl minimum sck low time mclk/12 m s sclk (cpol=0, cpha=0) sclk sclk sclk miso/ mosi ss (cpol=0, cpha=1) (cpol=1, cpha=0) (cpol=1, cpha=1) internal strobe for data capture msb 6 5 4 3 2 1 lsb figure 8. spi clocking scheme. TDA7503 13/26
general purpose i/o (gpio) interface timing characteristics mclk = 20mhz unit min. max. t god xti edge to gpio out valid (gpio out delay time) -- 26 ns t goh xti edge to gpio out not valid (gpio out hold time) 2 -- ns t gis gpio in valid to xti edge (gpio in set-up time) 10 -- ns t gih xti edge to gpio in not valid (gpio in hold time) 6 -- ns figure 10. gpio timing t t ad ds mclk xale xpsen opload address data t acc figure 9. timing diagram for external memory interface for the calculation of slowest access time allowed for a memory attached to the m8051, the following diagram illustrates the timing constraints. slowest access time allowed, t acc = 4*mclk - t ad -t ds , where the worst case address delay, t ad = 30 ns, and the worst case data setup time, t ds = 20 ns. micro memory interface TDA7503 14/26
debug port interface no. characteristics dclk = 40mhz unit min. max. 1 dbck rise time -- 3 ns 2 dbck fall time -- 3 ns 3 dbck low 40 -- ns 4 dbck high 40 -- ns 5 dbck cycle time 200 -- ns 6 dbrqn asserted to dbout (ack) asserted 5 t dsp -- ns 7 dbck high to dbout valid -- 42 ns 8 dbck high to dbout invalid 3 -- ns 9 dbin valid to dbck low (set-up) 15 -- ns 10 dbck low to dbin invalid (hold) 3 -- ns dbout (ack) asserted to first dbck high 2 tc -- ns dbout (ack) assertion width 4.5 t dsp -3 5t dsp +7 ns 11 last dbck low of read register to first dbck high of next command 7t dsp +10 -- ns 12 last dbck low to dbout invalid (hold) 3 -- ns dbsel setup to dbck t dsp ns TDA7503 15/26
figure 11. debug port serial clock timing. figure 12. debug port acknowledge timing. figure 13. debug port data i/o to status timing. figure 14. debug port read timing. figure 15. debug port dbck next command after read register timing. TDA7503 16/26
external memory interface (emi) dram mode characteristics timing mode 40mhz unit min. max. page mode cycle time slow fast 100 75 -- -- ns ns ras or rd assertion to data valid slow fast -- -- 159 109 ns ns cas assertion to data valid slow fast -- -- 65 40 ns ns column address valid to data valid slow fast -- -- 80 55 ns ns cas assertion to data active 0 -- ns ras assertion pulse width (note 1) (page mode access only) slow fast 264 189 -- -- ns ns ras assertion pulse width (single access only) slow fast 164 114 -- -- ns ns ras or cas negation to ras assertion slow fast 120 70 -- -- ns ns cas assertion pulse width slow fast 65 40 -- -- ns ns last cas assertion to ras negation (page mode access only) slow fast 60 35 -- -- ns ns note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6. dram refresh timing characteristics timing mode 40mhz unit min. max. ras negation to ras assertion slow fast 143 93 -- -- ns ns cas negation to cas assertion slow fast 118 68 -- -- ns ns refresh cycle time slow fast 325 225 -- -- ns ns ras assertion pulse width slow fast 166 116 -- -- ns ns ras negation to ras assertion for refresh cycle (note 1) slow fast 120 70 -- -- ns ns cas assertion to ras assertion on refresh cycle 18 -- ns ras assertion to cas negation on refresh cycle slow fast 160 110 -- -- ns ns ras negation to cas assertion on a refresh cycle slow fast 114 64 -- -- ns ns cas negation to data not valid 0 -- ns note: 1. happens when a refresh cycle is followed by an access cycle. TDA7503 17/26
external memory interface (emi) sram mode characteristics 40mhz unit min. max. address valid and cs assertion pulse width 89 -- ns address valid to rd or wr assertion 23 -- ns rd or wr assertion pulse width 45 -- ns rd or wr negation to rd or wr assertion 39 -- ns rd or wr negation to address not valid 5 -- ns address valid to input data valid -- 72 ns rd assertion to input data valid -- 35 ns rd negation to data not valid (data hold time) 0 -- ns address valid to wr negation 73 -- ns data setup time to wr negation 32 -- ns data hold time from wr negation 5 -- ns wr assertion to data valid -- 18 ns wr negation to data high-z (note 1) -- 23 ns wr assertion to data active 5 -- ns TDA7503 18/26
dra [8:0] row address 1 column address 1 column address 2 row address 2 ras cas drd nibble 1 nibble 2 drd [3:0] figure 18. dram read cycle. add. [7:0] data add. [13:8] sra_d [7:0] sra_d [13:8] ale drd figure 16. external memory interface sram read cycle. add. [7:0] data add. [13:8] sra [7:0] sra [13:8] ale dwr figure 17. external memory interface sram write cycle. TDA7503 19/26
row address 1 column address 1 column address 2 row address 2 dwr cas dra [8:0] ras nibble 1 nibble 2 drd[3:0] figure 19. dram write cycle. functional description. the aladdin ic broken up into two distinct blocks. one block contains the two dsp cores and their associated peripherals. the other contains the m8051 core and its associated peripherals. the interface between the two blocks is the host in- terface. 24-bit dsp core. the two dsp cores are used to process the con- verted analog audio data coming from the codec chip via the sai and return it for analog conversion. functions such as volume, tone, bal- ance, and fader control, as well as spatial en- hancement and general purpose signal process- ing may be performed by the dsps. some capabilities of the dsps are listed below: single cycle multiply and accumulate with con- vergent rounding and condition code genera- tion 2 x 56-bit accumulators double precision multiply scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations fast or long interrupts possible programmable interrupt priorities and masking 8 each of address registers, address offset registers and address modulo registers linear, reverse carry, multiple buffer modulo, multiple wrap-around modulo address arith- metic post-increment or decrement by 1 or by offset, index by offset, predecrement address repeat instruction and zero overhead do loops hardware stack capable of nesting combina- tions of 7 do loops or 15 interrupts/subrou- tines bit manipulation instructions possible on all registers and memory locations. also jump on bit test. 4 pin serial debug interface debug ccess to all internal registers, buses and memory locations 5 word deep program address history fifo hardware and software breakpoints for both program and data memory accesses debug single stepping, instruction injection and disassembly of program memory dsp peripherals there are a number of peripherals that are tightly coupled to the two dsp cores. except for the memories and the host interface, a single periph- eral is multiplexed to both of the dsp cores. in the case of the host interface(hi), for dsp to mi- cro communication, there are two identical pe- ripheral blocks providing the same function to both dsp cores. each of the peripherals are listed below and described in the following sec- tions. 256 x 24-bit x-ram. 256 x 24-bit y-ram. 768 x 24-bit program ram (1280 x 24 for dsp1) 256 x 24-bit data x-rom. 256 x 24-bit data y-rom. TDA7503 20/26
64 x 24-bit boot rom. serial audio interface (sai) multiplexed to both dsps. synchronous serial interface (ssi) multiplexed to both dsps. xchg interface for dsp to dsp communica- tion. host interface (hi) for dsp to micro communi- cation. external memory interface (dram/sram) multiplexed to both dsps for time-delay. single debug port multiplexed to both dsps. cordic arithmetic unit data and program memory both dsp0 and dsp1 have an identical set of data and program memories attached them. each of the memories are described below and it is implied that there are two of each type, one set connected to dsp0 and the other to dsp1. the only exception is the case of the p-ram where dsp0 has a 768 x 24-bit pram and dsp1 has a 1280 x 24-bit pram. 256 x 24-bit x-ram (xram) this is a 256 x 24-bit single port sram used for storing coefficients. the 16-bit xram address, xabx(15:0) is generated by the address genera- tion unit of the dsp core. the 24-bit xram data, xdbx(23:0), may be written to and read from the data alu of the dsp core. the xdbx bus is also connected to the internal bus switch so that it can be routed to and from all peripheral blocks. 256 x 24 bit y-ram (yram) this is a 256 x 24-bit single port sram used for storing coefficients. the 16-bit address, yabx(15:0) is generated by the address genera- tion unit of the dsp core. the 24-bit data, ydbx(23:0), is written to and read from the data alu of the dsp core. the ydbx bus is also con- nected to the internal bus switch so that it can be routed to and from other blocks. 768 x 24-bit program ram (pram 1280 x 24-bit for dsp1) this is a 768 x 24-bit single port sram used for storing and executing program code. the 16-bit pram address, pabx(15:0) is generated by the program address generator of the dsp core for instruction fetching, and by the agu in the case of the move program memory (movem) instruc- tion. the 24-bit pram data (program code), pdbx(23:0), can only be written to using the movem instruction. during instruction fetching the pdbx bus is routed to the program decode controller of the dsp core for instruction decod- ing. 256 x 24-bit x-rom (xrom) this is a 256 x 24-bit factory programmed x- rom. the 16-bit address, xabx(15:0) is gener- ated by the agu unit. the 24-bit data is multi- plexed onto the xdbx bus when the address is valid. 256 x 24-bit y-rom (yrom) this is a 256 x 24-bit factory programmed y- rom. the 16-bit address, yabx(15:0) is gener- ated by the agu unit. the 24-bit data is multi- plexed onto the ydbx bus when the address is valid. 128 x 24-bit bootstrap rom (prom) this is a 128 x 24-bit factory programmed boot rom used for storing the program sequence for initializing the dsp. essentially this consists of a routine that is called when the m8051 requests that a dsp image be sent via the host interface. it is the task of the boot code to read the data be- ing sent by the micro from the host interface fifo and store it in pram, xram, yram, and/or external dram. operating mode register the operating mode register contains one bit to choose between boot mode (always from the host interface) or normal mode (execution from pram). this bit will be set when the dsp is reset (by writing to the rsdspx bit in the clkcntl register). it must be cleared by the boot code to enable execution from pram. dsp memory maps the dsp memory maps are shown in figure 26. serial audio interface (sai) the sai is used to deliver digital audio to the dsps from an external source. once processed by the dsps, it can be returned through this inter- face. there is only one sai on the chip that can be accessed by either dsp. the features of the sai are listed below. five synchronized stereo data transmission lines four synchronized stereo data reception lines slave operating mode, all clock lines are in- puts TDA7503 21/26
dsp1 $0000 x-space p-space $ffff x-ram p-ram x-rom not accessible not accessible y-space y-ram y-rom not accessible boot-space not accessible boot-rom $04ff $0500 $003f $00ff $ffc0 $0040 $01ff $0200 $0100 $ffbf dsp0 $0000 x-space p-space $ffff x-ram p-ram x-rom not accessible not accessible x-peripherals y-space y-ram y-rom not accessible boot-space not accessible boot-rom $003f $00ff $ffc0 $0040 $02ff $0300 $0100 $ffbf $01ff $0200 x-peripherals figure 20. dsp1 and dsp0 memory spaces. transmit and receive interrupt logic triggers on left/right data pairs receive and transmit data registers have two locations to hold left and right data. synchronous serial interface (ssi) the ssi is used for communication with devices with a conventional serial interface (not i2s ste- reo serial audio interface). the ssi shares some pins with the sai. when the ssi is activated, some of the sai pins are switched from the sai to the ssi. the sai and ssi can operate in paral- lel. the features of the ssi are listed below. slave operating mode, fsync and ssisck are inputs. data sizes of 8, 16, and 24 bits are supported. frame sync (fsync) and sck (ssisck) sig- nals connected to both the receiver and trans- mitter. normal mode or network mode possible. xchg interface (dsp to dsp exchange inter- face) the exchange interface peripheral provides bidi- rectional communication between dsp0 and dsp1. both 24 bit word data and four bit flag data can be exchanged. a fifo is utilized for re- ceived data. it minimizes the number of times an exchange interrupt service routine would have to be called if multi-word blocks of data were to be received. the transmit fifo is in effect the receive fifo of the other dsp and is written di- rectly by the transmitting dsp. the features of the xchg are listed below. 10 word xchg receive fifo on both dsps four flags for each xchg for dsp to dsp signaling condition flags can optionally trigger interrupts on both dsps host interface(hi) the dsps communicate with the 8051 through the host interface. there is a separate hi for each of the dsps. two host interfaces are in- cluded. hi0 for host to dsp0 communication, and hi1 for host to dsp1 communication. the TDA7503 22/26
features of the hi are listed below. 8 word host receive fifo - dsp side 4 word host receive fifo - host (8051) side two flags for each hi for dsp to host signal- ing (can optionally trigger interrupts) command vector register allows host to trig- ger any dsp vectored interrupt dram/sram interface (emi) the external dram/sram interface is viewed as a memory mapped peripheral. data transfers are performed by moving data into/from data regis- ters and the control is exercised by polling status flags in the control/status register or by servicing interrupts. an external memory write is executed by writing data into the emi data write register. an external memory read operation is executed by either writing to the offset register or reading the emi data read register, depending on the configuration. the features of the emi are listed below. data bus width fixed at 4 bits for dram and 8 bits for sram. data word length choices of 16 or 24 bits. nine dram address lines means 218 = 256kb addressable dram. refresh rate for dram can be chosen among eight divider factor. sram relative addressing mode with multi- plexed address/data lines; 214= 16kb ad- dressable sram. four sram timing choices. two read offset registers. debug interface the debug port is multiplexed to both of the dsp cores via a select pin. only one dsp can be de- bugged at a time. the debug logic is contained in the core design of the dsp. the features of the debug port are listed below: breakpoint logic trace logic single stepping instruction injection program disassembly cordic co-processor the cordic co-processor is used to convert rectangular to polar coordinates. . the cordic unit has an 18 bit data path throughout. when reading 24 bit words from the dsp the upper 6 bits are truncated. when writing to the dsp the upper 6 bits are zeroed. either dsp may write an x and y coordinate to the cordic unit and, 17 clock cycles later, the magnitude and angle information will be available from the cordic unit. 8051 embedded microcontroller the microcontroller serves as the on-chip system controller and operates from 64k of external eprom with 1k of internal ram. in addition, it contains a small program in internal ram that al- lows the micro to program the external eprom. the micro will boot a network interface program from external eprom. if a command to program the eprom is received from the network then the following sequence will be initiated: the micro will read a rom image from the network via a net- work chip attached to the micro's spi. then the micro will switch to running out of internal ram and begin programming the external eprom with the image read from the network. this allows the personality of the system to be set after the system has been manufactured. the external eprom also holds the dsp programs and initial- izing values. the micro will copy these images to the dsp via an on-chip host interface (hi). in addition to the 8051 core the following mem- ory and control functions are required: internal memory interface to 256 bytes of sin- gle port static ram and 768 bytes of aux- ram external memory interface to eprom and memory mapped peripheral i/o host interface for micro to dsp communica- tion serial peripheral interface (spi) control interface for interrupts and gpio pll clock oscillator internal memory interface the 8051 requires an internal memory interface to connect to the internal 256 ram locations and the 768 auxiliary ram. micro memory interface the 8051 core requires an external memory inter- face to connect to external program memory and memory mapped peripherals. this is imple- mented like the standard 80c51 port 2/port 0 multiplexed 16 bit address/8 bit data bus. . the signals rd, wr, xpsen, and xale will also be output. the external memory interface must also have circuitry to program the external eprom (or any non-volatile memory) in-circuit. this means that the normal operation of the external memory interface must be altered to handle the program timing of the eprom. by treating the port 2/port 0 pins as gpio the programming can be TDA7503 23/26
achieved in software. when this mode is entered instruction execution is switched to internal aux- ram. serial peripheral interface the 8051 core requires a serial interface to re- ceive commands and data over the lan. during an spi transfer, data is transmitted and received simultaneously. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. a slave select line allows in- dividual selection of a slave spi device. the ss pin will act as a gpio when the spi is in master mode or the spi is disabled. when an spi transfer occurs an 8-bit word is shifted out one data pin while another 8-bit char- acter is simultaneously shifted in a second data pin. the central element in the spi system is the shift register and the read data buffer. the sys- tem is single buffered in the transfer direction and double buffered in the receive direction. control interface the 8051 requires a set of external general pur- pose input/output lines, two external interrupt lines, and a reset line. these signals are used by external devices to signal events to the 8051. the gpio lines are implemented as the 8051's port 1 gpio. the two external interrupts are connected to the int0 and int1 lines on the micro. the re- set pin is used to reset the micro. pll clock oscillator the pll clock oscillator can accept an external clock at xti or it can be configured to run an in- ternal oscillator when a crystal is connected across pins xti & xto. there is an input divide block idf (1 -> 32) at the xti clock input and a multiply block mf (33 -> 128) in the pll loop. hence the pll can multiply the external input clock by a ratio mf/idf to generate the internal clock. this allows the internal clock to be within 1 mhz of any desired frequency even when xti is much greater than 1 mhz. it is recommended that the input clock is not divided down to less than 1 mhz as this reduces the phase detector's update rate. the clocks to the dsp and the 8051 can be se- lected to be either the vco output divided by 2 or 4 respectively, or be driven by the xti pin di- rectly. the crystal oscillator and the pll will be gated off when entering the power-down mode (by setting bit 1 of the pcon register). m8051 interrupts the m8051 core provides for 5 interrupt sources, int1, int0, timer1, timer0, and serial data. there exists a corresponding interrupt en- able register and interrupt priority register. TDA7503 24/26
dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.003 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.00 0.472 e 0.50 0.019 e 16.00 0.630 e1 14.00 0.551 e3 12.00 0.472 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.0393 k 3.5 (min.), 7 (max.) tqfp100 a a2 a1 seating plane c 25 26 50 51 75 76 100 d3 d1 d e 1 b tqfp100m 0.076mm .003 inch pin 1 identification k l l1 e3 e1 e outline and mechanical data TDA7503 25/26
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com TDA7503 26/26

▲Up To Search▲

Price & Availability of TDA7503

	To Download TDA7503 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .